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Sheet目录3871

33页 34页 35页 36页 [37页]38页 39页 40页 41页

2010 Microchip Technology Inc.

DS39774D-page 131

PIC18F85J11 FAMILY

TABLE 11-3:

PORTA FUNCTIONS

TABLE 11-4:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Pin Name

Function

TRIS

Setting

I/O

Type

Description

RA0/AN0

RA0

DIG

LATA<0> data output; not affected by analog input.

TTL

PORTA<0> data input; disabled when analog input enabled.

AN0

ANA

A/D Input Channel 0. Default input configuration on POR; does not

affect digital output.

RA1/AN1

RA1

DIG

LATA<1> data output; not affected by analog input.

TTL

PORTA<1> data input; disabled when analog input enabled.

AN1

ANA

A/D Input Channel 1. Default input configuration on POR; does not

affect digital output.

RA2/AN2/VREF-RA2

DIG

LATA<2> data output; not affected by analog input.

TTL

PORTA<2> data input. Disabled when analog functions enabled.

AN2

ANA

A/D Input Channel 2. Default input configuration on POR.

VREF-

ANA

A/D and comparator low reference voltage input.

RA3/AN3/

VREF+

RA3

DIG

LATA<3> data output; not affected by analog input.

TTL

PORTA<3> data input; disabled when analog input enabled.

AN3

ANA

A/D Input Channel 3. Default input configuration on POR.

VREF+

ANA

A/D and comparator high reference voltage input.

RA4/T0CKI

RA4

DIG

LATA<4> data output.

PORTA<4> data input; default configuration on POR.

T0CKI

Timer0 clock input.

RA5/AN4

RA5

DIG

LATA<5> data output; not affected by analog input.

TTL

PORTA<5> data input; disabled when analog input enabled.

AN4

ANA

A/D Input Channel 4. Default configuration on POR.

RA6/OSC2/

CLKO

RA6

DIG

LATA<6> data output; disabled when FOSC2 Configuration bit is set.

TTL

PORTA<6> data input; disabled when FOSC2 Configuration bit is set.

OSC2

ANA

Main oscillator feedback output connection (HS and HSPLL modes).

CLKO

DIG

System cycle clock output, FOSC/4 (EC and ECPLL modes).

RA7/OSC1/

CLKI

RA7

DIG

LATA<7> data output; disabled when FOSC2 Configuration bit is set.

TTL

PORTA<7> data input; disabled when FOSC2 Configuration bit is set.

OSC1

ANA

Main oscillator input connection (HS and HSPLL modes).

CLKI

ANA

Main external clock source input (EC and ECPLL modes).

Legend:

O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,

TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

PORTA

RA7(1)

RA6(1)

RA5

RA4

RA3

RA2

RA1

RA0

LATA

LATA7(1)

LATA6(1)

LATA5

LATA4

LATA3

LATA2

LATA1

LATA0

TRISA

TRISA7(1)

TRISA6(1)

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

ADCON1

—

VCFG1

VCFG0

PCFG3

PCFG2

PCFG1

PCFG0

Legend: — = Unimplemented, read as ‘0’, x = Don’t care. Shaded cells are not used by PORTA.

Note 1:

These bits are enabled depending on the oscillator mode selected. When not enabled as PORTA pins,

they are disabled and read as ‘x’.

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